An elementary SRAM-type cell is a volatile memory cell, that is to say, a memory cell that loses its data in the event of a power cut, but that offers a very rapid access speed and infinite cycling.
A nonvolatile elementary memory cell, for example a memory cell of EEPROM type, allows the data item to be preserved in the event of a power cut but cannot be cycled indefinitely.
A memory cell associating an elementary cell of SRAM type and one or more nonvolatile cells allows accumulation of the levels of performance of the two approaches, namely the speed and the infinite endurance of the SRAM memory and the nonvolatility of the nonvolatile memory.
Under normal operating condition, a data item is written and read to/from a memory cell of this kind in the elementary cell of SRAM type. On the other hand, notably when there is a power cut, the content of the SRAM elementary cell is transferred to the nonvolatile elementary memory cell(s) associated therewith.
Then, notably when power returns, the data contained in the nonvolatile memory cell(s) are reloaded into the corresponding SRAM elementary memory cell.
Architectures of such memory cells associating SRAM memory and nonvolatile memory are described in U.S. Pat. Nos. 4,132,905, 4,467,451, 4,980,859, 7,164,608 and 8,018,768.
Among these documents, the first four describe structures of memory cells associating an elementary SRAM-type cell and several nonvolatile cells, with the notable drawback of complexity of structure and/or the need to have an SRAM cell that supports high voltage and/or large constraints for the reloading phase of the SRAM cell.
U.S. Pat. No. 8,018,768 describes a memory cell having an elementary SRAM-type cell and a single nonvolatile elementary memory cell of Flash type. The cell structure described in this document is complex notably on account of the presence of an additional inverter connected between the Flash elementary cell and the SRAM cell. This additional inverter, controlled by the nonvolatile elementary memory cell, is used when the data item is reloaded into the SRAM memory, in order to pull the output of an inverter of the SRAM cell to ground, while the input of this additional inverter is pulled to the supply voltage by means of the Flash cell.